Free GATE ECE mock test — 65 questions, GATE marking

One GATE EC paper in the real exam format: 65 questions across one timed section, 3 hr on a server-controlled clock.

About the real exam GATE Electronics & Communication — a high-volume gateway to M.Tech at IISc/IITs and core electronics, semiconductor, VLSI, telecom and PSU careers.

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3 hr65 questions · 1 section
About the exam

What the GATE EC asks of you

GATE Electronics and Communication Engineering (EC) is among the most competitive papers in the GATE family, with one of the largest candidate pools each year. It is the gateway to M.Tech at IISc, IITs and NITs across VLSI Design, Communication Systems, Signal Processing, RF and Microwave, Control, and Microelectronics, and a recruitment screen for core-electronics and telecom PSUs (BEL, ISRO, DRDO, BSNL, ECIL) as well as power-sector PSUs that recruit EC graduates. The paper spans eight sections — engineering mathematics, networks/signals & systems, electronic devices, analog circuits, digital circuits, control systems, communications, and electromagnetics — with 65 questions in 180 minutes for 100 marks.

Eight official sections from the GATE 2026 EC syllabus, modelled at topic level: (1) Engineering Mathematics — linear algebra, calculus, ODE/PDE, vector analysis, complex analysis, probability (13 marks, 15.3%). (2) Networks, Signals & Systems — network theorems, transient/AC steady-state, two-port, Fourier/Laplace/Z-transform, LTI systems (15 marks, 17.6%, heaviest). (3) Electronic Devices — semiconductor physics, carrier transport, P-N junction, BJT, MOSFET, LED, photodiode (7 marks, 8.2%). (4) Analog Circuits — diodes, BJT/MOSFET amplifiers, current mirrors, op-amps, active filters, oscillators (11 marks, 12.9%). (5) Digital Circuits — number systems, Boolean/K-map, combinational/sequential logic, ADC/DAC, memories, computer organization (9 marks, 10.6%). (6) Control Systems — transfer function, time/frequency response, Routh/Nyquist/Bode/root locus, compensators, state space (9 marks, 10.6%). (7) Communications — random processes, AM/FM, information theory, PCM, digital modulation, matched filter, error coding (11 marks, 12.9%). (8) Electromagnetics — Maxwell's equations, plane waves, transmission lines, S-parameters, waveguides, antennas (10 marks, 11.8%).

Who sits the GATE EC

  • B.E./B.Tech students in Electronics, Electronics & Communication, or Electronics & Telecommunication in their pre-final or final year
  • Aspirants targeting M.Tech at IISc, IITs, NITs in VLSI, Communications, Signal Processing, RF/Microwave, Microelectronics
  • Core-electronics and R&D job seekers — ISRO, DRDO, BEL, ECIL, BSNL, and semiconductor/EDA firms that screen on GATE
  • Working professionals moving into chip design, embedded systems, or communications roles
  • Repeaters aiming to improve a previous GATE EC rank with a structured, syllabus-aligned plan

How people prepare for it

  1. 1Build a 6-9 month plan: 3-4 months first-pass concept coverage, 2-3 months problem-solving depth, 1-2 months full-length mocks and revision
  2. 2Prioritise heavy sections: Networks/Signals & Systems (15), Engineering Math (13), Analog (11), Communications (11) together cover 50 of 85 core marks
  3. 3Practice numerical answer type (NAT) problems daily — no negative marking, reward accuracy
  4. 4Master transfer function manipulation, Fourier/Laplace/Z-transforms, two-port parameters, and small-signal analysis — these recur across sections
  5. 5Solve at least 15 years of previous-year GATE EC questions; pattern recognition is the biggest score multiplier
  6. 6Take a full-length 3-hour mock paper weekly from month 5; review every wrong answer the same day
  7. 7Maintain a formula notebook — EC spans 200+ standard relations across devices, signals, control, comm and fields
  8. 8Do not neglect General Aptitude — 15 marks, easily gained with light practice
120K+
Annual candidates
180 minutes
Paper duration
65
Total questions
100
Total marks
85 (8 sections)
Core subject marks
-1/3, -2/3 (MCQ only)
Negative marking
Virtual on-screen
Calculator
~15-16% of test-takers
Qualifying rate

Figures about the real exam, as recorded in the Myndaq course. They describe the real sitting, not this free mock paper - check current details with the exam body before you book.

What it opens up

  • Apply for M.Tech at IISc, IITs, NITs across VLSI, Communications, Signal Processing, RF/Microwave, Microelectronics, Control
  • Qualify for R&D recruitment at ISRO, DRDO, BEL, ECIL and other core-electronics establishments
  • Qualify for PhD admission with research fellowship at premier institutes
  • Eligible for Junior Research Fellowship (JRF) in DRDO, ISRO, BARC and other R&D labs
  • Foundation for international M.S. applications — GATE score recognised by NUS, NTU Singapore and select European universities
  • Strengthened core EC fundamentals applicable to semiconductor, chip-design, embedded, and telecom industry roles

Figures above are as reported for the cycle named in each row and are refreshed each cycle. Sourced, dated facts for this exam (official links on every row) are on the GATE EC course page.

The published paper

The paper, start to finish

01GATE EC — Full Mock65q · 3 hrScored out of 100 marks; wrong answers can cost marks
Calculator

Navigation: move freely between questions within a section.

Try the question style

Sample questions with worked answers

8 original practice questions written by Myndaq in the GATE EC style. They are not taken from this mock paper or from official past papers. Try each one, then open the answer.

  1. Question 1General AptitudeOne correct answer

    Pipe P alone can fill a tank in 12 hours and pipe Q alone can fill it in 18 hours. Both pipes are opened together on an empty tank, and after 3 hours pipe P is shut. How many more hours does Q alone need to fill the tank completely?

    1. 9
    2. 10
    3. 10.5
    4. 12
    Show answer and explanation

    Answer: C

    In one hour P fills 1/12 and Q fills 1/18 of the tank. In the first 3 hours together they fill 3/12 + 3/18 = 1/4 + 1/6 = 5/12 of the tank, so 7/12 remains.

    Q alone fills 1/18 per hour, so it needs (7/12) ÷ (1/18) = 18 × 7/12 = 10.5 hours. 12 hours would be right only if the first 3 hours had filled one third of the tank (18 × 2/3 = 12), but they fill 5/12. In 10 hours Q fills only 10/18 = 5/9 of the tank, which is less than the 7/12 still needed. 9 hours would fill only half the tank.

  2. Question 2Engineering MathematicsType a numeric answer

    The solution of the differential equation y'' + 4y' + 4y = 0 with y(0) = 1 and y'(0) = 0 is evaluated at t = 1. The value of y(1), rounded to two decimal places, is ______.

    Show answer and explanation

    Answer: 0.40 to 0.41

    The characteristic equation r² + 4r + 4 = (r + 2)² = 0 has the repeated root r = -2, so y(t) = (A + Bt)e^(-2t).

    y(0) = A = 1. Differentiating, y'(t) = Be^(-2t) - 2(A + Bt)e^(-2t), so y'(0) = B - 2A = 0 and B = 2. Hence y(t) = (1 + 2t)e^(-2t).

    Check: y' = -4t e^(-2t) and y'' = (-4 + 8t)e^(-2t); then y'' + 4y' + 4y = (-4 + 8t - 16t + 4 + 8t)e^(-2t) = 0, and y'(0) = 0.

    y(1) = 3e^(-2) = 3 × 0.1353 ≈ 0.406.

  3. Question 3Networks, Signals and SystemsType a numeric answer

    A DC circuit has a node X and a ground node. Between X and ground there are three branches: (i) an ideal 24 V source in series with a 6 Ω resistor, with the positive terminal of the source towards X; (ii) a 3 Ω resistor; (iii) an ideal 2 A current source that drives current from ground into node X. A variable load resistor RL is then connected between X and ground.

    The maximum power, in watts, that can be delivered to RL is ______.

    Show answer and explanation

    Answer: 18

    Find the Thevenin equivalent seen by RL. With RL removed, KCL at X (currents leaving X) gives (V - 24)/6 + V/3 - 2 = 0. Multiplying by 6: V - 24 + 2V - 12 = 0, so 3V = 36 and Vth = 12 V.

    To find Rth, replace the voltage source by a short and the current source by an open circuit: Rth = 6 || 3 = 18/9 = 2 Ω.

    Maximum power transfer occurs at RL = Rth = 2 Ω, giving Pmax = Vth²/(4Rth) = 144/8 = 18 W. Check: the load current is 12/4 = 3 A and 3² × 2 = 18 W. Leaving out the current source would give Vth = 8 V and only 8 W.

  4. Question 4Networks, Signals and SystemsOne or more correct answers

    A continuous-time system has input x(t) and output y(t) = t·x(t). Which of the following properties does the system have?

    1. Linear
    2. Time-invariant
    3. Causal
    4. BIBO stable
    5. Memoryless
    Show answer and explanation

    Answer: A, C, E

    Linear: an input a·x1(t) + b·x2(t) gives t(a·x1 + b·x2) = a·y1(t) + b·y2(t), so superposition holds.

    Not time-invariant: the input x(t - t0) gives t·x(t - t0), but the shifted output is y(t - t0) = (t - t0)·x(t - t0). These differ, because the gain t depends on time.

    Causal and memoryless: y at time t depends only on x at the same instant t.

    Not BIBO stable: the bounded input x(t) = 1 gives y(t) = t, which grows without bound. So A, C and E are correct.

  5. Question 5Analog CircuitsOne correct answer

    An NMOS common-source amplifier has its source grounded, drain resistor RD = 5 kΩ to a 12 V supply and a DC gate-source voltage of 2 V. The transistor has threshold voltage VT = 1 V, obeys ID = (k/2)(VGS - VT)² in saturation with k = 2 mA/V², and channel-length modulation is negligible. The small-signal voltage gain from gate to drain, with no external load, is

    1. -5 V/V
    2. -10 V/V
    3. -20 V/V
    4. +10 V/V
    Show answer and explanation

    Answer: B

    Bias: ID = (2/2)(2 - 1)² = 1 mA, so VDS = 12 - 1 × 5 = 7 V. Since 7 V is greater than VGS - VT = 1 V, the transistor is in saturation and the square-law model applies.

    Transconductance: gm = k(VGS - VT) = 2 × 1 = 2 mA/V (equivalently 2ID/(VGS - VT) = 2 mA/V).

    Gain = -gm × RD = -2 mA/V × 5 kΩ = -10 V/V. The common-source stage inverts, so +10 is wrong; -5 comes from wrongly taking gm = ID/(VGS - VT), and -20 from doubling gm.

  6. Question 6Digital CircuitsOne correct answer

    A four-variable function is given as F(W, X, Y, Z) = Σm(1, 3, 4, 6, 9, 11, 12, 14), with W as the most significant bit. Its minimal sum-of-products form is

    1. X'Z + XZ'
    2. X'Z' + XZ
    3. W'X'Z + XZ'
    4. X'Y'Z + XZ'
    Show answer and explanation

    Answer: A

    Write each minterm in binary as WXYZ. Minterms 1, 3, 9 and 11 are 0001, 0011, 1001 and 1011: in all four X = 0 and Z = 1 while W and Y take every combination, so together they reduce to X'Z.

    Minterms 4, 6, 12 and 14 are 0100, 0110, 1100 and 1110: in all four X = 1 and Z = 0, which reduces to XZ'.

    So F = X'Z + XZ', the XOR of X and Z. Option B is the XNOR, the complement of F. Option C misses minterms 9 and 11 (it forces W = 0), and option D misses minterms 3 and 11 (it forces Y = 0).

  7. Question 7Control SystemsOne or more correct answers

    A unity negative-feedback system has open-loop transfer function G(s) = K / [s(s + 2)(s + 5)] with K > 0. Which of the following statements are TRUE?

    1. The closed-loop system is stable for K = 50.
    2. At K = 70 the closed-loop system has a pair of poles on the imaginary axis at s = ±j√10.
    3. The closed-loop system is stable for every K > 0.
    4. For K = 80, exactly one closed-loop pole lies in the right half of the s-plane.
    Show answer and explanation

    Answer: A, B

    The characteristic equation is s(s + 2)(s + 5) + K = s³ + 7s² + 10s + K = 0. Routh array: s³ row 1, 10; s² row 7, K; s¹ row (70 - K)/7; s⁰ row K. All first-column entries are positive only when 0 < K < 70, so K = 50 gives a stable system (A true) and stability does not hold for every K (C false).

    At K = 70 the s¹ row vanishes; the auxiliary equation 7s² + 70 = 0 gives s = ±j√10. Indeed s³ + 7s² + 10s + 70 = (s + 7)(s² + 10), so B is true.

    At K = 80 the first column is 1, 7, -10/7, 80. There are two sign changes, so two poles lie in the right half-plane, not one. D is false.

  8. Question 8CommunicationsType a numeric answer

    A conventional AM (DSB with full carrier) transmitter is modulated by a single sinusoidal tone. The unmodulated carrier power is 500 W and the total transmitted power is 580 W. The modulation index, rounded to two decimal places, is ______.

    Show answer and explanation

    Answer: 0.56 to 0.57

    For single-tone AM the total power is Pt = Pc(1 + μ²/2). So 580 = 500(1 + μ²/2), which gives μ²/2 = 80/500 = 0.16 and μ² = 0.32.

    μ = √0.32 ≈ 0.566. A common slip is to take μ²/2 = 0.16 as μ = 0.16 or to forget the factor of 2 (which would give μ = 0.4); neither satisfies the power equation.

Marks and results

What you get back

What this free mock returns

You get your raw marks and per-section scores. No scaled score, band, rank or percentile is estimated for this paper.

  • Scored out of 100 raw marks, with per-section totals.
  • Wrong answers can cost marks where the paper defines it - the per-section marks in the paper map are the marks the scorer applies.

How the real GATE EC is scored

Top GATE EC rank-holders typically score 70-85 marks (out of 100) for AIR under 100, unlocking IISc Bangalore and IIT Bombay/Delhi/Madras M.Tech in VLSI, Communications, and Signal Processing, plus shortlisting at ISRO, DRDO and BEL. Marks of 50-70 with AIR 100-1500 generally place candidates into IIT/NIT M.Tech and core-electronics R&D interviews. The qualifying cut-off is around 25 marks; roughly 15-16% of EC candidates qualify each year.

  • 800+ / 1000 (~70+ / 100, AIR < 100)Strong shot at IISc Bangalore, IIT Bombay/Delhi/Madras M.Tech in VLSI, Communications, Signal Processing, RF. Top R&D shortlist (ISRO, DRDO, BEL).
  • 700 - 800 / 1000 (AIR 100 - 800)M.Tech at IIT Kanpur/Kharagpur/Roorkee/Hyderabad/Guwahati. Core-electronics PSU and R&D shortlist.
  • 600 - 700 / 1000 (AIR 800 - 3000)M.Tech at top NITs (Trichy, Warangal, Surathkal) and IIITs. Broader R&D and semiconductor-firm screening.
  • 500 - 600 / 1000 (AIR 3000 - 12000)M.Tech at state-tier NITs and reputed universities; junior R&D and embedded-systems roles.
  • Qualifying (25 - 40 / 100, no rank)Valid GATE scorecard — eligible for teaching/research assistantship and JRF screening at DRDO/ISRO/BARC.

Context only - this free mock returns: You get your raw marks and per-section scores. No scaled score, band, rank or percentile is estimated for this paper.

Fidelity

How this mirrors the real format

  • The paper structure is the real format: a single timed section, 65 questions in total.
  • Timing is server-controlled for the full 3 hr -- closing the tab does not pause the clock, exactly like our paid mock series.
  • Marking follows the published paper: the per-section marks shown in the paper map are the marks the scorer applies.
  • Navigation is free within a section: you can review and change answers before you submit.
  • An on-screen calculator is provided in the sections where the exam allows one.

"Real format" means the paper shape, timing, marking and navigation above - not the official exam software, its visual identity, or any affiliation with the exam body.

Be clear about this

What differs or is limited

  • This free mock follows the same paper shape, timing, marking scheme and navigation as our paid GATE Electronics and Communication Engineering mock series. It is scored automatically. It does not include tutor explanations, analysis dashboards or practice content.
  • Includes the virtual calculator and free navigation, as in the real exam.
One attempt

One attempt, explicitly

Adding this mock to your account is free and reversible - you can change the exam any time before you begin. Only the confirmed Begin action uses your one attempt. No retake, no reset, no card.

Before you begin

Device and setup checklist

  • A stable internet connection for the full duration.
  • An on-screen calculator is provided where the exam allows one.
  • A laptop or desktop is recommended for the closest exam experience.
Questions

Frequently asked

How many attempts do I get?
One. Every account gets exactly one free mock, on one exam. You can change the chosen exam freely until you begin the paper; after that the attempt is permanently used and there is no retake.
What does the result include?
You get your raw marks and per-section scores. No scaled score, band, rank or percentile is estimated for this paper.
Is the timing real?
Yes. The paper runs 3 hr on a server-controlled clock, section by section. Closing the tab does not pause it.
Do I need to pay or add a card?
No. The free mock needs only a Myndaq account. The paid course unlocks explanations, practice content and the full mock series.

About the real GATE EC

Do I need to study General Aptitude separately?
Yes — General Aptitude carries 15 marks (10 questions), more than most single technical sections. Most EC toppers score 12+ on GA. Treat it as a 30-day sprint in months 7-8.
Is there overlap between GATE EC and GATE EE (Electrical)?
Significant overlap in Engineering Math, Signals & Systems, Control Systems, and Analog/Digital Electronics. Electronic Devices, Communications, and Electromagnetics (waves/antennas) are EC-focused; Power Systems and Machines are EE-exclusive. Roughly 35-40% syllabus overlap.
Which section carries the most weight?
Networks, Signals and Systems is the single heaviest section (~15 marks), combining circuit analysis with continuous/discrete-time signal processing and LTI systems. Engineering Mathematics is second (~13 marks).
Can I clear GATE EC with self-study?
Yes — most EC toppers report self-study using standard textbooks (Sedra-Smith, Razavi, Oppenheim, Nagrath-Gopal, Sadiku, Haykin) with 8-10 years of PYQ practice. Coaching adds structure but is not required.
How important are numerical answer type (NAT) questions?
Very — NAT carries 30-40% of total marks, has no negative marking, and rewards genuine problem-solving. EC toppers often report NAT accuracy of 75-85% on test day.
Is the GATE 2026 syllabus the same as 2027?
Likely yes. The EC syllabus has been stable for several years with only minor wording changes. IIT Madras (the 2027 organising institute) is expected to publish the 2027 syllabus in August 2026; historically the changes are minimal (<5%).
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